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RELEASED REFERENCE DESIGN PMC-1991709 ISSUE 1
PM5351 S/UNI-155-TETRA
S/UNI 155 TETRA WITH S/UNI ATLAS REFERENCE DESIGN
PM5351
S/UNI-155 TETRA WITH S/UNI ATLAS
REFERENCE DESIGN
RELEASED ISSUE 1: SEPTEMBER 2001
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1991709 ISSUE 1
PM5351 S/UNI-155-TETRA
S/UNI 155 TETRA WITH S/UNI ATLAS REFERENCE DESIGN
PUBLIC REVISION HISTORY Issue No. 1 Issue Date September 2001 Details of Change Document Created
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RELEASED REFERENCE DESIGN PMC-1991709 ISSUE 1
PM5351 S/UNI-155-TETRA
S/UNI 155 TETRA WITH S/UNI ATLAS REFERENCE DESIGN
CONTENTS 1 2 3 4 5 DEFINITIONS ...........................................................................................1 FEATURES...............................................................................................2 APPLICATIONS........................................................................................3 REFERENCES .........................................................................................4 APPLICATION EXAMPLES ......................................................................5 5.1 6 7 ATM SWITCH PORT CARD ..........................................................5
BLOCK DIAGRAM....................................................................................6 FUNCTIONAL DESCRIPTION .................................................................7 7.1 7.2 PM5351 S/UNI-155-TETRA ...........................................................7 PM7324 S/UNI-ATLAS...................................................................7 7.2.1 NOTE ON S/UNI-ATLAS THROUGHPUT ...........................8 7.2.2 INGRESS SRAM.................................................................8 7.2.3 EGRESS SRAM ..................................................................9 7.3 7.4 COMPACT PCI INTERFACE .........................................................9 MICROPROCESSOR PORT CPLD...............................................9 7.4.1 PHY OUTPUT SELECT ....................................................10 7.4.2 BOARD RESET................................................................. 11
8
IMPLEMENTATION DESCRIPTION.......................................................12 8.1 8.2 SHEET 1, ROOT DRAWING .......................................................12 SHEET 2-3, SUNI-TETRA BLOCK ..............................................12 8.2.1 SHEET 2: TETRA BLOCK.................................................12 8.2.2 SHEET 3: TETRA SUPPLY FILTERING............................12
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RELEASED REFERENCE DESIGN PMC-1991709 ISSUE 1
PM5351 S/UNI-155-TETRA
S/UNI 155 TETRA WITH S/UNI ATLAS REFERENCE DESIGN
8.3
SHEETS 4 - 7, SUNI-ATLAS BLOCK..........................................12 8.3.1 SHEET 4: SCI-PHY MASTER INTERFACE ......................12 8.3.2 SHEET 5: SCI-PHY SLAVE INTERFACE..........................12 8.3.3 SHEET 6: INGRESS AND EGRESS SRAM INTERFACES12 8.3.4 SHEET 7: MICROPROCESSOR INTERFACE..................13
8.4
PCI INTERFACE BLOCK.............................................................13 8.4.1 SHEET 8: PLX9050 PCI INTERFACE...............................13 8.4.2 SHEET 9 MICROPROCESSOR PORT CPLD ..................13
8.5 8.6 8.7 9 10 11 12 13
SHEET 10, OPTICS BLOCK........................................................13 SHEET 11, INGRESS_SRAM......................................................13 SHEET 12, EGRESS_SRAM.......................................................14
SCHEMATICS ........................................................................................15 LAYOUT..................................................................................................16 BILL OF MATERIALS .............................................................................17 VHDL CODE ...........................................................................................19 EEPROM CONTENTS ...........................................................................21
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RELEASED REFERENCE DESIGN PMC-1991709 ISSUE 1
PM5351 S/UNI-155-TETRA
S/UNI 155 TETRA WITH S/UNI ATLAS REFERENCE DESIGN
LIST OF FIGURES
FIGURE 1 - ATM SWITCH USING S/UNI-155-TETRA AND S/UNI-ATLAS .......5 FIGURE 2 - BLOCK DIAGRAM OF ATLAS-TETRA REFERENCE DESIGN .....6 FIGURE 3 - OPERATION OF THE REFERENCE DESIGN...............................7 FIGURE 4 - PHY CHANNEL SELECTION .......................................................10
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RELEASED REFERENCE DESIGN PMC-1991709 ISSUE 1
PM5351 S/UNI-155-TETRA
S/UNI 155 TETRA WITH S/UNI ATLAS REFERENCE DESIGN
LIST OF TABLES TABLE 1 TABLE 2 - CPLD OUTPUT CHANNEL SELECT REGISTER 0X00H ............10 - PHY CHANNEL SELECT .............................................................10
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RELEASED REFERENCE DESIGN PMC-1991709 ISSUE 1
PM5351 S/UNI-155-TETRA
S/UNI 155 TETRA WITH S/UNI ATLAS REFERENCE DESIGN
1
DEFINITIONS CPCI Compact PCI. An adapted specification from the Peripheral Component Interconnect (PCI) Specification 2.1 or later using a mechanical form factor suitable for tugged environments. Fault Management. The mechanism used by the network to inform management entities and other network equipment of faults within the network. Form factor for fibre optic connectors which feature receive and transmit interfaces in a single plug. Operations, Administration, and Maintenance. The maintenance of VCs within the network. Peripheral Component Interconnect. A specification typically used to interconnect PC chipsets. Performance Management. The mechanism used by the network to monitor the performance parameters of a particular VC. Virtual Connection. This refers to either a Virtual Path Connection (VPC) or a Virtual Channel Connection (VCC) within a physical link. Virtual Channel Connection. A virtual connection between two network elements. A virtual channel connection is normally a constituent member of a virtual path connection, where the VPC consists of one or more VCCs. This is sometimes known as an F5 connection. Virtual Path Connection. A virtual connection between two network elements. A virtual path connection may span one or more physical links. This is sometimes known as an F4 connection.
FM
MT-RJ OAM PCI PM
VC
VCC
VPC
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RELEASED REFERENCE DESIGN PMC-1991709 ISSUE 1
PM5351 S/UNI-155-TETRA
S/UNI 155 TETRA WITH S/UNI ATLAS REFERENCE DESIGN
2
FEATURES The following features are supported by this reference design. Note that the list of features is not exhaustive, nor does it represent the full capabilities of the TETRA or the ATLAS. * * * * * * * Support for up to 8K VCs (Virtual Connections) Ingress header translation Ingress cell rate policing (per-VC and per-PHY) OAM-FM on all VCs OAM-PM on 256 bidirectional VCs Egress header translation Four STS-3c interfaces using MT-RJ fibre optic connectors
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RELEASED REFERENCE DESIGN PMC-1991709 ISSUE 1
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S/UNI 155 TETRA WITH S/UNI ATLAS REFERENCE DESIGN
3
APPLICATIONS * ATM Switch Port Card
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RELEASED REFERENCE DESIGN PMC-1991709 ISSUE 1
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S/UNI 155 TETRA WITH S/UNI ATLAS REFERENCE DESIGN
4
REFERENCES
1. PMC-1971154, "S/UNI-ATLAS Datasheet", Issue 7, Jan 2000. 2. PMC-1971240, "S/UNI-TETRA Datasheet", Issue 7, Feb 2000. 3. PICMG 2.0 R2.1, "CompactPCI Specification", September 2, 1997 4. PMC-1980585, "S/UNI-ATLAS Programmers Guide and Example Software", Issue 2, Feb 1999. 5. PMC-1981505, "S/UNI-ATLAS Datasheet Errata", Issue 1, June 2001. 6. PMC-1980583,"Switch Port (SPORT) Card Reference Design", Issue 3, Nov 1999. 7. PMC-1990330, "ATM Switch Using S/UNI-ATLAS, QRT, and QSE Reference Design", Issue 2, July 1999. 8. ATM Forum, "ATM Forum Traffic Management Specification Version 4.1", Mar 1999.
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RELEASED REFERENCE DESIGN PMC-1991709 ISSUE 1
PM5351 S/UNI-155-TETRA
S/UNI 155 TETRA WITH S/UNI ATLAS REFERENCE DESIGN
5 5.1
APPLICATION EXAMPLES ATM Switch Port Card The figure below shows a complete ATM switch using the S/UNI 155 TETRA and S/UNI ATLAS on a line card. This design is explained in detail in PMC-1980583 "Switch Port (SPORT) Card Reference Design" and PMC-1990330 "ATM Switch Using S/UNI-ATLAS, QRT, and QSE Reference Design" Figure 1 - ATM Switch Using S/UNI-155-TETRA and S/UNI-ATLAS
ATLAS-TETRA Reference Design CARD #1
Timing Card
4 x 155 Mbps
PM5351 S/UNITETRA
UL2
PM7324 S/UNI-ATLAS
UL2
CARD #4
Traffic Manager
4 x 155 Mbps
PM5351 S/UNITETRA
UL2
PM7324 S/UNI-ATLAS
UL2
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RELEASED REFERENCE DESIGN PMC-1991709 ISSUE 1
PM5351 S/UNI-155-TETRA
S/UNI 155 TETRA WITH S/UNI ATLAS REFERENCE DESIGN
6
BLOCK DIAGRAM Figure 2 - Block Diagram of ATLAS-TETRA Reference Design
4 x OC-3 I/Fs
19.44 MHz Oscillator RFCLK TFCLK
PM5351 S/UNI-TETRA
ISYSCLK ESYSCLK ATLAS_RFCLK ATLAS_TFCLK
PHY_SEL_CLK
ISRAMCLK0
SSRAM 128Kx36
ISRAMCLK0
SSRAM 128Kx36
XC95216
PHY_SEL[1..0]
PM7324 S/UNI-ATLAS
SSRAM 128Kx36
IFCLK OFCLK
UL2/PL2 BUS SLAVE
PLX9054 I/O ACCELERATOR
PCI CONTROL SIGNALS DATA BUS ADDRESS BUS
CPCI Connector J1
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ESRAMCLK
50MHz Oscillator & Driver
UL2/PL2 BUS MASTER
RELEASED REFERENCE DESIGN PMC-1991709 ISSUE 1
PM5351 S/UNI-155-TETRA
S/UNI 155 TETRA WITH S/UNI ATLAS REFERENCE DESIGN
7
FUNCTIONAL DESCRIPTION The S/UNI-155-TETRA with S/UNI-ATLAS reference board is designed to demonstrate the features of the PM5351 S/UNI-155-TETRA and the PM7324 S/UNI-ATLAS on a small form factor PCB. As a result, it is a subset of a complete ATM switch (see Section 5.1). On the receive side, the S/UNI TETRA takes SONET/SDH traffic from 4xOC3 PHYs and extracts ATM cells from the SONET/SDH frame for subsequent processing by the S/UNI-ATLAS device. Once the ATM cells are passed to the ATLAS via the UL2 master interface, they are processed according to their corresponding VC table. The processed cells are then passed to the slave UL2 interface that is looped back into the egress direction of the ATLAS device. After egress processing occurs, the cells are passed back to the S/UNI-TETRA for insertion into a SONET/SDH frame and subsequent transmission over the optical medium. Figure 3 - Operation of the Reference Design
4 x 155 Mbps
PM5351 S/UNITETRA
UL2
PM7324 S/UNI-ATLAS
UL2
7.1
PM5351 S/UNI-155-TETRA The TETRA is responsible for all physical layer functions. It features internal clock and data recovery for four 155 Mbps optical interfaces. MT-RJ connectors are used to interface to the optical fiber. For more information on the PM5351 S/UNI-TETRA, please refer to the S/UNI-TETRA Datasheet, PMC-1971240.
7.2
PM7324 S/UNI-ATLAS The PM7324 S/UNI-ATM Layer Solution (S/UNI-ATLAS) is a PMC-Sierra standard product that implements the following ATM Layer functions:
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RELEASED REFERENCE DESIGN PMC-1991709 ISSUE 1
PM5351 S/UNI-155-TETRA
S/UNI 155 TETRA WITH S/UNI ATLAS REFERENCE DESIGN
* * * * *
OAM processing according to ITU-T I.610 1998. Header Translation on full VPI/VCI address range. Prepend/Postpend tagging. Cell rate policing according to ITU-T I.371 using the Generic Cell Rate Algorithm. Per-PHY queuing to prevent head-of-line blocking.
In the receive direction, the S/UNI ATLAS takes cells from the S/UNI-155-TETRA and performs a lookup based on the PHY number, VPI, and VCI to identify the associated connection. Once the connection is identified, the cell is processed according to the configuration of the connection. In this application, the ATLAS can perform header translation, per-PHY and per-VC policing, performance monitoring, and fault management. In the transmit direction, a direct lookup is performed by the ATLAS to identify the connection. The cell is then processed according to the configuration in the context table for that connection. Header translation and OAM processing can be done at the egress. For a more detailed description of the S/UNI-ATLAS, please refer to the S/UNIATLAS Datasheet, PMC-1971154. 7.2.1 Note on S/UNI-ATLAS Throughput This reference design uses a 50 Mhz clock for the UL2 bus. However, due to a throughput issue in the S/UNI-ATLAS, as explained in PMC-1981505 "S/UNIATLAS Datasheet Errata", there are certain configurations that do not allow maximum throughput through the device. One workaround is to clock the ISYSCLK at 59.5 Mhz. On this reference design this is not possible as both the ISYSCLK and ESYSCLK are clocked from the same source. The ESYSCLK is limited to a maximum clock frequency of 57 Mhz. In addition, if the clock frequency on ISYSCLK is increased beyond 52Mhz, the HALFSECCLK can no longer be generated internally (it will be faster than 1/2 Second) and must be sourced externally. A more detailed description of workaround options can be found in PMC-1981505 "S/UNI-ATLAS Datasheet Errata". 7.2.2 Ingress SRAM The Ingress VC Table is a 15-row 64 bit data structure which contains context information for up to 65536 connections. The Ingress VC Table is used for connection identification, connection configuration and cell processing functions.
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RELEASED REFERENCE DESIGN PMC-1991709 ISSUE 1
PM5351 S/UNI-155-TETRA
S/UNI 155 TETRA WITH S/UNI ATLAS REFERENCE DESIGN
The connection identification fields of the VC Table are located in the first two rows of the structure, and the remaining rows are used for connection configuration and cell processing. The Ingress VC Table is stored externally to the S/UNI-ATLAS in SRAM (Static Ram). The ingress SRAM data bus is 72 bits wide (8 bytes plus byte parity), with an address space of 20 bits (1M). This creates enough context address space for 64K VCs. The entire SRAM space does not have to be populated however. If less than 64K VCs are required, or a subset of ATLAS features is used, then the SRAM required is reduced. However, additional glue logic may be required to achieve the savings in SRAM. In this reference design, enough SRAM is used to provision up to 8K VCs. For the ATLAS, synchronous flow-through non-pipelined SRAMs must be used for both the Ingress and Egress. 7.2.3 Egress SRAM The Egress VC table is a 16-row 32-bit data structure which contains context information for up to 65536 connections. The Egress VC Table is used for connection identification, connection configuration and cell processing functions. The connection identification field of the Egress VC Table record is located in the first row of the structure, and the remaining rows are used for connection configuration and cell processing. Like the Ingress VC Table, the Egress VC Table is stored external to the S/UNIATLAS in SRAM. The egress SRAM data bus is 36 bits wide (4 bytes plus byte parity), with an address space of 20 bits (1M). This allows for 64K connections, as with the Ingress VC Table. In this design, enough SRAM is provided to provision up to 8K VCs. 7.3 Compact PCI Interface Microprocessor access to the devices on board is provided using a PLX 9050 PCI bridge chip between the compact PCI bus and the local microprocessor bus. An AMP HM 2mm connector is used in accordance with the CPCI standard. For more information on the pin functions refer to CompactPCI Specification [10]. 7.4 Microprocessor Port CPLD A Xilinx 95216 CPLD is used perform the following functions. * PHY output select
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RELEASED REFERENCE DESIGN PMC-1991709 ISSUE 1
PM5351 S/UNI-155-TETRA
S/UNI 155 TETRA WITH S/UNI ATLAS REFERENCE DESIGN
*
Board reset
7.4.1 PHY Output Select The CPLD allows the user to manually select which PHY the looped back data will be output to. Table 2 shows what values to write for each output channel. Figure 4 - PHY Channel Selection
4 x 155 Mbps
PM5351 S/UNITETRA
UL2
PM7324 S/UNI-ATLAS
UL2
IADDR<1..0>
CPLD
CHAN_SEL<1..0>
Table 1 below describes the function of bits in the Output Channel Select Register. Table 1 Bit 7..2 1 0 W W - CPLD Output Channel Select Register 0x00h Type Function NOT USED CHAN_SEL(1) CHAN_SEL(0) Default 0 0 0
CHAN_SEL [1..0] These bits are used to select the output PHY. Table 2 - PHY Channel Select
Output Channel 1
CHAN_SEL[1..0] 00
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RELEASED REFERENCE DESIGN PMC-1991709 ISSUE 1
PM5351 S/UNI-155-TETRA
S/UNI 155 TETRA WITH S/UNI ATLAS REFERENCE DESIGN
CHAN_SEL[1..0] 01 10 11
Output Channel 2 3 4
7.4.2 Board Reset The CPLD also performs a master reset on all of the devices (TETRA, ATLAS, PCI BRIDGE) when the reset button is pressed.
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RELEASED REFERENCE DESIGN PMC-1991709 ISSUE 1
PM5351 S/UNI-155-TETRA
S/UNI 155 TETRA WITH S/UNI ATLAS REFERENCE DESIGN
8
IMPLEMENTATION DESCRIPTION This section details the hardware on the S/UN-155-TETRA reference design, with reference to the schematics in Section 9.
8.1
Sheet 1, Root Drawing This sheet shows the interconnection between the functional blocks of the design.
8.2
Sheet 2-3, SUNI-TETRA Block
8.2.1 Sheet 2: TETRA Block Sheet 2 shows the S/UNI-TETRA and it's surrounding connections. A 19.44MHz oscillator provides timing reference for the S/UNI-TETRA. A 1K resistor is used to prevent latchup when VDD exceeds VBIAS. 8.2.2 Sheet 3: TETRA Supply Filtering Sheet 3 shows the power supply filtering for the S/UNI-TETRA. 8.3 Sheets 4 - 7, SUNI-ATLAS Block
8.3.1 Sheet 4: SCI-PHY Master Interface Sheet 4 shows the Ingress Input and Egress Output cell interfaces of the ATLAS. RPOLL and TPOLL pins are both set high to enable PHY polling. Source terminations are used. 8.3.2 Sheet 5: SCI-PHY Slave Interface Sheet 5 shows the Ingress Output and Egress Input cell interfaces of the ATLAS. J3 selects between UL2 polling mode and direct PHY mode. For normal operation, UL2 polling mode should be used. Y2 and U14 are the source for all 50MHz clocks on the board. Source terminations are used. 8.3.3 Sheet 6: Ingress and Egress SRAM Interfaces Sheet 6 shows the Ingress and Egress SRAM interfaces.
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RELEASED REFERENCE DESIGN PMC-1991709 ISSUE 1
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S/UNI 155 TETRA WITH S/UNI ATLAS REFERENCE DESIGN
8.3.4 Sheet 7: Microprocessor Interface Sheet 7 shows the ATLAS microprocessor interface. TP9 is provided to allow BUSYB to interrupt the microprocessor. This may be useful for SRAM access software routines. The HALFSECCLK input is tied low, since it is not required when ISYSCLK and ESYSCLK is 52, 50, or 25 MHz. A 1K resistor is used to prevent latchup when VDD exceeds VBIAS. If 5V tolerance is not required, VBIAS may be tied to 3.3V. 8.4 PCI INTERFACE Block
8.4.1 Sheet 8: PLX9050 PCI Interface Sheet 8 shows the PLX9050 PCI bridge chip and associated circuitry. U1 is a serial EEPROM used to provide configuration information to the PLX9050 on startup. Address and Data pins are non multiplexed. Separate RDB and WRB signals are provided and the clock output of the PLX9050 is buffered to drive the CPLD microprocessor interface. 10 Ohm stub terminations are provided as required by the CPCI specification. 8.4.2 Sheet 9 Microprocessor Port CPLD Sheet 9 shows the CPLD used to perform interrupt identification and PHY output select. Headers are provided to allow in system programming of the CPLD. The CPLD generates a free running clock for the JTAG interfaces of the ATLAS and TETRA. The free-run clock along with the TMS pin of these devices being tied high, continuously resets the JTAG circuitry ensuring proper operation. 8.5 Sheet 10, OPTICS Block Sheet 10 shows the four MT-RJ optical transceivers. TXD+/- signal traces are terminated near the optics using two 49.9 Ohm resistors and a DC biasing network. RXD+/- signal traces are terminated with a 100 Ohm resistor across RXD+/-. All differential pairs are kept equal length. 8.6 Sheet 11, INGRESS_SRAM Sheet 11 shows the connections to the ingress SRAM interface. There is enough SRAM to support 8K connections at the ingress. If more connections are required, this configuration would be maintained, and banks would be added using ISA[13:15]. For instance, to add a second bank of SRAM, ISA[13] would
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PM5351 S/UNI-155-TETRA
S/UNI 155 TETRA WITH S/UNI ATLAS REFERENCE DESIGN
be used to select the second bank. Terminations are not required if the SRAMs are placed close enough to the ATLAS. 8.7 Sheet 12, EGRESS_SRAM Sheet 12 shows the connections to the egress SRAM interface. There is enough SRAM to support 8K connections at the egress. If more connections are required, this configuration would be maintained, and banks would be added using ESA[13:15]. Terminations are not required if the SRAMs are placed close enough to the ATLAS. GSI Technology SRAMS are recommended and have been tested with the S/UNI-ATLAS.
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S/UNI 155 TETRA WITH S/UNI ATLAS REFERENCE DESIGN
9
SCHEMATICS
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8
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PAGE 8,9 PCI_INTERFACE
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H OCA ORDENB IWRENB OSOC ISOC PHY_SEL_DAT<1> PHY_SEL_DAT<0> PHY_SEL_CLK IADDR<0> IADDR<1> INGRESS_SRAM CSB_TETRA MD<31..0> MA<11..0> G ISADSB ISOEB ISRWB ISA<19..0> ISP<7..0> ISD<63..0> ISRAMCLK0 ISRAMCLK1 PAGE 4,5,6,7 SUNI_ATLAS ATLAS_ALE JTAG_CLK OCA ORDENB IWRENB OSOC ISOC PHY_SEL_DAT<1> PHY_SEL_DAT<0> PHY_SEL_CLK IADDR<0> IADDR<1> PAGE 11
H
WRB RDB TETRA_INTB ATLAS_INTB RESETB
CSB_TETRA
MD<31..0> MA<11..0>
CSB_ATLAS
ATLAS_ALE JTAG_CLK
G
WRB RDB
TETRA_INTB ATLAS_INTB RESETB
CSB_ATLAS
ATLAS_ALE CSB_ATLAS
F
RESETB ATLAS_INTB WRB RDB
7..0
ISRAMCLK0 ISRAMCLK1 ISD<63..0> ISD<63..0> ISP<7..0> ISP<7..0> ISA<19..0> ISA<19..0> ISRWB ISRWB ISOEB ISOEB ISADSB ISADSB
F
MD<31..0>
9..0
MA<11..0> IADDR<1> IADDR<0> PHY_SEL_CLK PHY_SEL_DAT<0> PHY_SEL_DAT<1> ISOC OSOC IWRENB ORDENB OCA
PAGE 2,3 E TETRA_BLOCK
E
MA<9..0> MD<7..0> RDB WRB TETRA_INTB RESETB CSB_TETRA PAGE 10 OPTICS_BLOCK TXD1P TXD1N RXD1P RXD1N SD1 TXD2P TXD2N RXD2P RXD2N C SD2 TXD3P TXD3N RXD3P RXD3N SD3 TXD4P TXD4N RXD4P RXD4N SD4 TXD1P TXD1N RXD1P RXD1N SD1 TXD2P TXD2N RXD2P RXD2N SD2 TXD3P TXD3N RXD3P RXD3N SD3 TXD4P TXD4N RXD4P RXD4N SD4 TXD1P TXD1N RXD1P RXD1N SD1
JTAG_CLK
JTAG_CLK
D
RFCLK RDAT<15..0> RPRTY RENB RCA RADDR<4..0>
RFCLK RDAT<15..0> RPRTY RENB RCA RADDR<4..0>
RFCLK RDAT<15..0> RPRTY RENB RCA RADDR<4..0>
D
RSOC TXD2P TXD2N RXD2P RXD2N SD2 TXD3P TXD3N RXD3P RXD3N SD3 TXD4P TXD4N RXD4P RXD4N SD4
RSOC
RSOC
TFCLK TDAT<15..0> TPRTY TENB TCA TADDR<4..0>
TFCLK TDAT<15..0> TPRTY TENB TCA TADDR<4..0>
TFCLK TDAT<15..0> TPRTY TENB TCA TADDR<4..0>
C
TSOC
TOSC
TSOC
B
ESRAMCLK ESD<31..0> ESP<3..0> ESA<19..0> ESRWB ESOEB ESADSB
ESRAMCLK ESD<31..0> ESP<3..0> ESA<19..0> ESRWB ESOEB ESADSB
B
PAGE 12 EGRESS_SRAM ESADSB ESOEB ESRWB ESA<19..0> ESP<3..0> ESD<31..0> ESRAMCLK A
DRAWING: TITLE=ATLAS_ROOT ABBREV=ATLAS_ROOT LAST_MODIFIED=Thu Jun 28 13:56:11 2001
PMC-Sierra, Inc.
DOCUMENT NUMBER: PMC-1991709 DOCUMENT ISSUE NUMBER: 1 TITLE: ATLAS TETRA PORT CARD ROOT DRAWING ENGINEER: RS ISSUE DATE: 01/06/26 REVISION NUMBER: 2 PAGE:1 2 1 OF 12 A
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REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
3.3 V HCMOS 19.44MHZ 3.3V 20PPM Y1
C224 0.01UF 8 C223 4 0.1UF 4.7UF
3.3 V
3D2> 3F2> 3H2> 3D6> 3F6> 3H6>
2.2 R83 C225
VDD
OUT
5 1
47 R78
GND NC/TS
QAVD<2..1> TAVD1<2..1> RAVD4<3..1> RAVD3<3..1> RAVD2<3..1> RAVD1<3..1>
K21 C17
1K RESISTOR PREVENTS LATCHUP WHEN VDD > VBIAS VCC
1.0K R64 0.1UF C180
+
G
G
U4
4 3 2 1 C208 0.22UF 4 C1 0.22UF 3 C6 0.22UF 2 C172 0.22UF 1
SBGA RAVD1<3..1> RAVD2<3..1> RAVD3<3..1> RAVD4<3..1> TAVD1<2..1> QAVD<2..1> VDD<36..1> BIAS1 BIAS2
ATB<4..1>
AC5
REFCLK CP<4..1> CN<4..1>
JTAG_CLK\I TCK TMS TDI
B8 B9 D10 A9 C9
9B10>
CP<4..1> CN<4..1>
100 R12
3.3 V
10F6>
RXD1P\I RXD1N\I SD1\I
50 OHM 50 OHM
E2 D1 E3 D3 E4
RXD1+ RXD1SD1 TXC1+ TXC1TXD1+ TXD1-
TDO TRSTB
F
10F6> 10F6>
RESETB\I
F
9B10>
TMOD TERR TEOP STPA DTCA/DTPA<4..1>
F22 D17 C18
10F6< 10C6> 10C6>
TXD1N\I
50 OHM
D2
B19
100
DTCA_TETRA<4..1> TDAT<15..0>\I
H22 J21 J23 47 R66
RXD2P\I RXD2N\I SD2\I
50 OHM 50 OHM
R11
G1 G2 J3 G3 H4
RXD2+ RXD2SD2 TXC2+ TXC2TXD2+ TXD2-
TDAT<15..0> TPRTY TSOC/TSOP TCA/PTPA TADR<4..0> TENB TFCLK
J22 K20
4D2> 4E2> 4E2> 4E2< 4E2> 4E2> 4E2<> 4E2> 4E2<> 4E2>
4
TPRTY\I TSOC\I TCA\I TADDR<4..0>\I TENB\I TFCLK\I 3.3 V
4.7K R65
E
10C6>
3
2
10D6< 10C6< 10F1> 10F1> 10F1>
TXD2P\I TXD2N\I
50 OHM 50 OHM
R8 R7
158 158 100
C8 C7
0.1UF 0.1UF
E1 F2
1
5G1>
T TP8 T TP6 T TP3 T
2 3 1 4
TP7
7 6 8 5
R9
158
C9
0.1UF
RN73 10
10G6<
TXD1P\I
50 OHM
R10
158
C10
0.1UF
C1
E
RXD3P\I RXD3N\I SD3\I
50 OHM 50 OHM
R6
W1 V2 U3 R2 R3
RXD3+ RXD3SD3 TXC3+ TXC3TXD3+ TXD3 RXD4+ RXD4SD4 TXC4+ TXC4TXD4+ TXD4-
S/UNI TETRA
PM5351
PHY_OEN
A19
RFCLK RENB RADR<4..0> RCA/PRPA RSOC/RSOP RPRTY RDAT<15..0> DRCA/DRP<4..1> REOP RERR RMOD RVAL
P21 P22
RFCLK\I RENB\I RADDR<4..0>\I
47 7 47 6 47 5
5G1> 4E10> 4E10<> 4E9> 4E10< 4E9< 4E10< 4E9<> 4E9>
D
10G1< 10F1< 10C1> 10C1> 10C1>
TXD3P\I TXD3N\I RXD4P\I RXD4N\I SD4\I
50 OHM 50 OHM 50 OHM 50 OHM
R4 R3
158 158
C5 C4 100 R5
0.1UF 0.1UF
T2 U1
N20 2 RN7 P23 3 RN7 T21 4 RN7
RCA\I RSOC\I RPRTY\I IRDAT<15..0> DRCA_TETRA<4..1>
D
AA1 Y2 W3 U4 V3
RDAT<15..0>\I
15 4 14 1 13 4 12 2 11 2 10 4 93 83 72 61 53 43 34 21 12 01
RN76 RN75 RN75 RN75 RN76 RN77 RN75 RN76 RN77 RN77 RN77 RN74 RN74 RN76 RN74 RN74 47 5 47 8 47 5 47 7 47 7 47 5 47 6 47 6 47 7 47 8 47 6 47 6 47 5 47 8 47 7 47 8
L23 L22 Y19 M22
10D1< 10C1<
TXD4P\I TXD4N\I
50 OHM 50 OHM
R2 R1
158 158
C3 C2
0.1UF 0.1UF
W2 Y1
C INTB TLDCLK<4..1> TSDCLK<4..1> TLD<4..1>
4 3 2 1 C10 B10 D11 A10 B11 C11 A11 B12 C12 4.7K R62
TETRA_INTB\I RESETB\I RDB\I WRB\I CSB_TETRA\I 3.3 V
9B2< 9B10> 8C3> 8C3> 8C3>
3 4
RSTB RDB WRB CSB ALE A<10> A<9> A<8> A<7..0> RAVS1<3..1> RAVS2<3..1> RAVS3<3..1> RAVS4<3..1> TAVS1<2..1> D<7..0> QAVS<2..1> VSS<36..1>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
4D9<
C
TSD<4..1>
4 3 2 1 AC11
9 8 2 4 7 1 3 6
TCLK TFPO TFPI RLDCLK<4..1>
RN6 4.7K
AB11 Y7 4.7K
D1
1 1 1 1 2 180 R21 180 R20 180 R19 180 R18
R79
10
5
D2 B
2
D3
2
NC<11..1>
2
G1 G2
74LPT541
1 19
RCLK<4..1> RFPO<4..1> RALRM<4..1> RALRM<4..1>
3.3 V
0.01UF C14
R63
D4
4.7K
18 17 16 15 14 13 12 11
SOIC U28 Y1 A1 Y2 A2 Y3 A3 Y4 A4 Y5 A5 Y6 A6 Y7 A7 Y8 A8
2 9 8 7..0
MA<9..0>\I
8E2>
1
2 3 4 5 6 7 8 9
4 3 2 1
CHIP_RES_NETWORK_8
TP2 T TP4 T TP1 T TP5 T B
RSDCLK<4..1> RLD<4..1> RSD<4..1>
MD<7..0>\I
7F6<> 8G1<> 9F10<>
PMC-Sierra, Inc.
DOCUMENT NUMBER: PMC-1991709 DOCUMENT ISSUE NUMBER: 1 DRAWING TITLE=TETRA_BLOCK ABBREV=TETRA_BLOCK LAST_MODIFIED=Thu Jun 28 13:59:04 2001 TITLE: ATLAS TETRA PORT CARD TETRA BLOCK ENGINEER: RS 3 2 ISSUE DATE: 01/06/26 REVISION NUMBER: 2 PAGE:2 1 OF 12 A
A
10
9
8
7
6
5
4
10
9
8
7
6
5
4
3
2
1
REVISIONS
ANALOG RECEIVE 1 3.3VF
0.1UF 3 C171
ZONE
RAVD1<3..1>
2G7<
REV
DESCRIPTION
DATE
APPR
H
H ANALOG RECEIVE 4
3.3VF
0.1UF C213
3
RAVD4<3..1>
2G7<
2 0.1UF C170
3.3 V
0.1UF C207
2
G
1 0.1UF C174
G
3.3 V
1 0.1UF 3 0.1UF C167 C206
ANALOG RECEIVE 2 3.3VF F
RAVD2<3..1>
2G7<
F ANALOG TRANSMIT
2 0.1UF C176
3.3VF
0.1UF C168
2
TAVD1<2..1>
2G7<
3.3 V E
0.1UF 1 0.1UF C169 C209 1
E
ANALOG RECEIVE 3 3.3VF
0.1UF C210 3
RAVD3<3..1>
2G7<
ANALOG QAVD
3.3 V
0.1UF C212
2
QAVD<2..1>
2G7<
D
D
2 0.1UF 1 C204 0.1UF 1 0.1UF C205 C214
3.3 V
C
C
SOT 3.3V U11 VCC
LT1121CST
4.7 R14 1
VIN GND
VOUT
3
3.3VF
47UF
47UF
10UF
+
+
C13
C12
C11
2
+
B 3.3 V
B
0.01UF
C179 0.01UF
C173 0.01UF
C178 0.01UF
0.01UF
C216 0.01UF
C175 0.01UF
C177 0.01UF
C211 0.01UF
C215
C217
PMC-Sierra, Inc.
PLACE DECOUPLING CAPS NEAR DIGITAL PWR PINS A DRAWING TITLE=TETRA_BLOCK ABBREV=TETRA_BLOCK LAST_MODIFIED=Thu Jun 28 13:59:06 2001 10 9 8 7 6 5 4 3 DOCUMENT NUMBER: PMC-1991709 DOCUMENT ISSUE NUMBER: 1 TITLE: ATLAS TETRA PORT CARD TETRA BLOCK ENGINEER: RS 2 ISSUE DATE: 01/06/26 REVISION NUMBER: 2 PAGE:3 1 OF 12 A
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
G
G
5G1>
ATLAS_TFCLK
F
3.3 V 3.3 V
F
R43
10K
10K
R44
U15
5G1> 2D3> 2D3< 2D3< 2D3< 2D3< 2D3< 2D3> 2D3< 2D3>
E
ATLAS_RFCLK RSOC\I RADDR<2>\I RADDR<1>\I RADDR<0>\I RADDR<4>\I RADDR<3>\I RCA\I RENB\I RPRTY\I
477 475 476 47 47
7 8
2 4 3
RN28 RN61 RN61 RN61
2
1RN28 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
D
U4 U3 V2 T2 T3 T4 R4 R3 T1 U2 U1 V3 W1 W2 W3 Y1 Y2 W4 Y3 AA1 AA2 Y4 AA3 AB1 AB2 AA4 AB3 AC1
RPOLL RFCLK RSOC RADDR<2>/RRDENB<4> RADDR<1>/RRDENB<3> RADDR<0>/RRDENB<2> RAVALID/RCA<4> RADDR<4>/RCA<3> RADDR<3>/RCA<2> RCA<1> RRDENB<1> RPRTY RDAT<15> RDAT<14> RDAT<13> RDAT<12> RDAT<11> RDAT<10> RDAT<9> RDAT<8> RDAT<7> RDAT<6> RDAT<5> RDAT<4> RDAT<3> RDAT<2> RDAT<1> RDAT<0>
TPOLL TFCLK TSOC TADDR<2>/TWRENB<4> TADDR<1>/TWRENB<3> TADDR<0>/TWRENB<2> TAVALID/TCA<4> TADDR<4>/TCA<3> TADDR<3>/TCA<2> TCA<1> TWRENB<1> TPRTY TDAT<15> TDAT<14> TDAT<13> TDAT<12> TDAT<11> TDAT<10> TDAT<9> TDAT<8> TDAT<7> TDAT<6> TDAT<5> TDAT<4> TDAT<3> TDAT<2> TDAT<1> TDAT<0>
L2 L1 M3 N2 N3 M1 P2 P3 N1 N4 M2 M4 G3 H4 G2 G1 H3 J4 H2 H1 J3 J2 J1 K3 L4 K2 K1 L3
10K
R45
RN603 2 RN27 RN60 4 RN27 3
4 RN28 1 RN27
6 47 7 47 547 647 547 847
TSOC\I TADDR<2>\I TADDR<1>\I TADDR<0>\I TADDR<4>\I TADDR<3>\I TCA\I TENB\I TPRTY\I
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
2E3< 2E3< 2E3< 2E3< 2E3< 2E3< 2E3> 2E3< 2E3<
E
4 5 47 RN27 8 47 RN60 1 7 47 RN58 2 5 47 RN58 4 5 47 RN254 RN25 3 6 47 RN58 3 6 47 RN592 7 47 2 7 47 RN25 1 847 RN25 847 RN59 1 RN26 4 547 3 6 47 RN26 6 47 RN59 3 5 47 RN59 4 2 7 47 RN26 1 847 RN26 747 RN60 2
D
2D1>
RDAT<15..0>\I
PM7324 S/UNI-ATLAS MASTER UTOPIA
C 47 8RN55 47 5RN55A 47 7RN57 SPARE
4.7K
TDAT<15..0>\I
1 4 2
2E3<
C
R42
C
B
B
DRAWING: TITLE=SUNI_ATLAS ABBREV=SUNI_ATLAS LAST_MODIFIED=Thu Jun 28 13:59:08 2001
PMC-Sierra, Inc.
A DOCUMENT NUMBER: PMC-1991709 DOCUMENT ISSUE NUMBER: 1 TITLE: ATLAS TETRA PORT CARD ATLAS SCI-PHY MASTER INTERFACE ENGINEER: RS 10 9 8 7 6 5 4 3 2 ISSUE DATE: 01/06/26 REVISION NUMBER: 2 PAGE:4 1 OF 12 A
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE
3.3 V
REV
DESCRIPTION
DATE
APPR
H
H
0.01UF
0.1UF
DECOUPLING FOR CLK DRIVER
C110
C107
3.3 V
C152
0.01UF
0.1UF
DECOUPLING FOR CLK DRIVER
C154
3.3 V
3.3 V SOIC20W U10 G
4 8 15 20
G
C108 0.01UF
PI49FCT3807
0.1UF
C109
8 4
VDD GND
OUT NC/TS
5 1
47 R37
MSTR_ATLAS_CLK
1
A
B0 B1 B2 B3 B4 B5 B6 B7 B8 B9
3 5 7 9 11 12 14 16 18 19
47 R38 4 5 47 RN57 1 8 47 RN57 4 5 47 RN56 3 6 47 RN56 2 7 RN56 RN52 47 2 7 47 3 6 47 RN55 2 7 47 RN55
PI49FCT3807
8PIN_DUAL 50.000MHZ 3.3V 100PPM Y2
SOIC20W U14
VCC VCC VCC VCC
VCC VCC VCC VCC
4 8 15 20
3.3 V
RN62 47 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9
3 5 7 9 11 12 14 16 18 19 1 2 3 4 8 7 6 5
1
A
ESYSCLK ISYSCLK ISRAMCLK1\I ISRAMCLK0\I ESRAMCLK\I PHY_SEL_CLK\I OFCLK
7E5< 7E5< 11D10< 11F10< 12E10< 9C10<
TFCLK\I RFCLK\I ATLAS_TFCLK ATLAS_RFCLK
2E3< 2D3< 4F10< 4E9<
GND GND GND GND GND
GND GND GND GND GND
F
2 6 10 13 17 2 6 10 13 17
F
E
IFCLK E
3.3 V PRTY 3.3 V
10K R40
J3 NOTE - SET TO HIGH FOR NORMAL OPERATION
1 2 3
HEADER3
9C2<
OSOC\I OCA\I ORDENB\I IADDR<1>\I IADDR<0>\I IWRENB\I ISOC\I
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 V29 Y30 Y31 W29 AA31 Y29 W28 W30 W31 V30 U28 U29 N28 M30 M31 N29 N30 N31 P29 R28 P30 R29 R30 R31 T28 T29 T30 T31
10K
D
9C2< 9D2> 9D2> 9D2>
U15
IPOLL IADDR<2>/IWRENB<4> IADDR<1>/IWRENB<3> IADDR<0>/IWRENB<2> IAVALID/ICA<4> IADDR<4>/ICA<3> IADDR<3>/ICA<2> IWRENB<1> ICA<1> IFCLK ISOC IPRTY IDAT<15> IDAT<14> IDAT<13> IDAT<12> IDAT<11> IDAT<10> IDAT<9> IDAT<8> IDAT<7> IDAT<6> IDAT<5> IDAT<4> IDAT<3> IDAT<2> IDAT<1> IDAT<0>
R41
D
9D2> 9C2>
C
OTSEN ORDENB OCA OFCLK OSOC OPRTY ODAT<15> ODAT<14> ODAT<13> ODAT<12> ODAT<11> ODAT<10> ODAT<9> ODAT<8> ODAT<7> ODAT<6> ODAT<5> ODAT<4> ODAT<3> ODAT<2> ODAT<1> ODAT<0>
AA30 Y28 AB31 AA29 AB30 AA28 AG31 AF29 AF30 AF31 AE29 AD28 AE30 AE31 AD29 AC28 AD30 AD31 AC29 AC30 AC31 AB29
RN521 RN54 RN54 RN30 RN30 RN54 RN54 RN30 RN30 RN53 RN53 RN29 RN29 RN53 RN29 RN29 RN53
1 2 3 4 3 4 1 2 1 3 3 4 2 1 2 4
847 8 7 6 5 6 5 8 7 8 6 6 5 7 8 7 5
47 47 47 47 47 47 47 47 47 47 47 47 47 47 47 47
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C
PM7324 S/UNI-ATLAS SLAVE UTOPIA
9C2< 9C2<
PHY_SEL_DAT<0>\I PHY_SEL_DAT<1>\I
0 1
DAT<15..0> B B
DRAWING: TITLE=SUNI_ATLAS ABBREV=SUNI_ATLAS LAST_MODIFIED=Thu Jun 28 13:59:10 2001
PMC-Sierra, Inc.
A DOCUMENT NUMBER: PMC-1991709 DOCUMENT ISSUE NUMBER: 1 TITLE: ATLAS TETRA PORT CARD ATLAS SCI-PHY SLAVE INTERFACE ENGINEER: RS 10 9 8 7 6 5 4 3 2 ISSUE DATE: 01/06/26 REVISION NUMBER: 2 PAGE:5 1 OF 12 A
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
U15 G
ISD<63> ISD<62> ISD<61> ISD<60> ISD<59> ISD<58> ISD<57> ISD<56> ISD<55> ISD<54> ISD<53> ISD<52> ISD<51> ISD<50> ISD<49> ISD<48> ISD<47> ISD<46> ISD<45> ISD<44> ISD<43> ISD<42> ISD<41> ISD<40> ISD<39> ISD<38> ISD<37> ISD<36> ISD<35> ISD<34> ISD<33> ISD<32> ISD<31> ISD<30> ISD<29> ISD<28> ISD<27> ISD<26> ISD<25> ISD<24> ISD<23> ISD<22> ISD<21> ISD<20> ISD<19> ISD<18> ISD<17> ISD<16> ISD<15> ISD<14> ISD<13> ISD<12> ISD<11> ISD<10> ISD<9> ISD<8> ISD<7> ISD<6> ISD<5> ISD<4> ISD<3> ISD<2> ISD<1> ISD<0> ISP<7> ISP<6> ISP<5> ISP<4> ISP<3> ISP<2> ISP<1> ISP<0> ISA<19> ISA<18> ISA<17> ISA<16> ISA<15> ISA<14> ISA<13> ISA<12> ISA<11> ISA<10> ISA<9> ISA<8> ISA<7> ISA<6> ISA<5> ISA<4> ISA<3> ISA<2> ISA<1> ISA<0> ISRWB ISOEB ISADSB
ISD<63..0>\I
AG1 AG2 AF4 AG3 AH1 AJ5 AH6 AK5 AL5 AJ6 AK6 AL6 AJ7 AH8 AK7 AL7 AJ8 AH9 AK8 AL8 AJ9 AK9 AL9 AJ10 AH11 AK10 AL10 AJ11 AH12 AK11 AL11 AJ12 AH13 AK12 AL12 AJ13 AK13 AL13 AJ14 AK14 AH15 AJ15 AL16 AK16 AJ16 AH16 AL17 AK17 AJ17 AK18 AH17 AJ18 AL19 AK19 AJ19 AL20 AK20 AH19 AJ20 AL21 AK21 AH20 AJ21 AL22 AD3 AE1 AE2 AD4 AE3 AF1 AF2 AF3 AJ23 AL24 AK24 AH23 AJ24 AL25 AK25 AH24 AJ25 AL26 AK26 AJ26 AL27 AK27 AH26 AJ27 AH31 AG29 AF28 AG30 AJ22 AL23 AK23 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
11D10<>
G
12F3<>
ESD<31..0>\I
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 B19 A19 C18 B18 D17 C17 A16 B16 C16 D16 A15 B15 C15 B14 D15 C14 A13 B13 C13 A12 B12 D13 C12 A11 B11 D12 C11 A10 B10 D11 C10 A9 D19 B20 A20 C19 D9 C8 A7 B7 D8 C7 A6 B6 C6 A5 B5 D6 D1 E3 F4 E2 E1 F3 F2 F1 B8 C9 A8
F
E
12D3<>
ESP<3..0>\I
3 2 1
12F10<
ESA<19..0>\I0
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
D
12E10< 12E10< 12D10<
ESADSB\I ESRWB\I ESOEB\I
ESD<31> ESD<30> ESD<29> ESD<28> ESD<27> ESD<26> ESD<25> ESD<24> ESD<23> ESD<22> ESD<21> ESD<20> ESD<19> ESD<18> ESD<17> ESD<16> ESD<15> ESD<14> ESD<13> ESD<12> ESD<11> ESD<10> ESD<9> ESD<8> ESD<7> ESD<6> ESD<5> ESD<4> ESD<3> ESD<2> ESD<1> ESD<0> ESP<3> ESP<2> ESP<1> ESP<0> ESA<19> ESA<18> ESA<17> ESA<16> ESA<15> ESA<14> ESA<13> ESA<12> ESA<11> ESA<10> ESA<9> ESA<8> ESA<7> ESA<6> ESA<5> ESA<4> ESA<3> ESA<2> ESA<1> ESA<0> ESADSB ESRWB ESOEB
F
E
D ISP<7..0>\I
11C10<>
ISA<19..0>\I
11H10<
C
C
ISRWB\I ISOEB\I ISADSB\I
11D10< 11D10< 11D10<
B
PM7324 S/UNI-ATLAS SRAM INTERFACE
B DRAWING: TITLE=SUNI_ATLAS ABBREV=SUNI_ATLAS LAST_MODIFIED=Thu Jun 28 13:59:12 2001
PMC-Sierra, Inc.
A DOCUMENT NUMBER: PMC-1991709 DOCUMENT ISSUE NUMBER: 1 TITLE: ATLAS TETRA PORT CARD ATLAS SRAM INTERFACES ENGINEER: RS 10 9 8 7 6 5 4 3 2 ISSUE DATE: 01/06/26 REVISION NUMBER: 2 PAGE:6 1 OF 12 A
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
G
G
1K RESISTOR PREVENTS LATCHUP WHEN VDD > VBIAS VCC F
1.0K R39 0.1UF
F
U15
8E2>
MA<11..0>\I
11 10 9 8 7 6 5 4 3 2 1 0 C23 B23 A23 C22 D21 B22 A22 C21 D20 B21 A21 C20 A24 C24 B24 D23 A25 AK22
E
8D1>
ATLAS_ALE\I
8C3> 8C3> 8C3> 9B10>
CSB_ATLAS\I RDB\I WRB\I RESETB\I
D<15> D<14> A<11> D<13> A<10> D<12> A<9> D<11> A<8> D<10> A<7> A<6> D<9> A<5> D<8> A<4> D<7> A<3> D<6> A<2> D<5> A<1> D<4> A<0> D<3> D<2> ALE D<1> CSB D<0> RDB WRB INTB RSTB IDREQ HALFSECCLK EDREQ BUSYB
J31 J30 J29 H31 H30 J28 H29 G31 G30 H28 G29 F31 F30 F29 E31 E30 K31 K30 L28 K29
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MD<31..0>\I
C111
2B3<> 8G1<> 9F10<>
3.3 V
B25
VDD<40-1>
5G4> 5G4>
U15 VBIAS
M28 L31 L30 M29 L29
3.3 V
ESYSCLK ISYSCLK
B9 AH21
PM7324 ESYSCLK ISYSCLK
ATLAS_INTB\I TP9 T
9B2<
TDO TDI TCK TMS TRSTB POWER BLOCK GND<48-1>
JTAG_CLK\I RESETB\I
9B10> 9B10>
E
PM7324 S/UNI-ATLAS POWER BLOCK
PM7324 S/UNI-ATLAS MICROPROCESSOR INTERFACE
D
D
C
C
3.3 V
0.01UF
C122 0.01UF
C115 0.01UF
C112 0.01UF
C143 0.01UF
C120 0.01UF
C121 0.01UF
C142 0.01UF
C118 0.01UF
C119 0.01UF
C123
B 3.3 V
0.01UF C114 0.01UF C139 0.01UF C138 0.01UF C140 0.01UF C116 0.01UF C141 0.01UF C117 0.01UF C144 0.01UF C145 0.01UF
DECOUPLING FOR ATLAS 1 CAP EVERY OTHER POWER PIN DRAWING: TITLE=SUNI_ATLAS ABBREV=SUNI_ATLAS LAST_MODIFIED=Thu Jun 28 13:59:14 2001
B
C113
PMC-Sierra, Inc.
A DOCUMENT NUMBER: PMC-1991709 DOCUMENT ISSUE NUMBER: 1 TITLE: ATLAS TETRA PORT CARD ATLAS MICRO INTERFACE AND POWER ENGINEER: RS 10 9 8 7 6 5 4 3 2 ISSUE DATE: 01/06/26 REVISION NUMBER: 2 PAGE:7 1 OF 12 A
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
CPCI CONNECTOR J1
5V SIGNALLING
VCC U5 VDD<1> VDD<2> VDD<3> VDD<4> VDD<5> VDD<6> VDD<7> VDD<8> VDD<9> VDD<10>
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 28 23 16 1 10 27 41 50 66 81 103 121 146 91 90 89 88 87 86 85 84 83 82 79 78 77 76 75 74 73 72 71 70 69 62 61 60 59 58 57 56 55 54 53 52 92 93 94 95 96 97 98 100 101 102 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 122 49 48 47 46 137 136 135 134 133 132 63 130 131 138 139 140 141 123 124 127 126 125 128 129 64 68 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11
VCC
VCC VCC RN79
5 6 7 8 5 6 7 8
4.7K RN78
5 6 7 8
4.7K
4.7K RN80
5 6 7 8
RN84
4.7K
G 3.3 V PCI_AD<31..0> PCI_CBE<3..0> RN13 RN13 RN13 RN12 RN12 RN12 RN12 RN11 RN11 RN11 RN10 RN10 RN10 RN10 RN9 RN90 RN5 RN5 RN5 RN4 RN4 RN4 RN4 RN3 RN3 RN2 RN2 RN2 RN2 RN1 RN1 RN1 RN11 RN9 RN5 RN3 RN90 RN8 RN8 RN8 RN90 RN3 RN8 RN90 RN9 RN1 RN13 RN9
3 2 1 4 3 2 1 4 2 1 4 3 2 1 4 1 3 2 1 4 3 2 1 4 1 4 3 2 1 4 3 2 3 3 4 2 2 1 2 3 4 3 4 3 2 1 4 1
G DATA BUS
4 3 2 1
4 3 2 1
15 14 13 12
11 10 9 8
4 3 2 1
7 6 5 4
3 2 1 0
4 3 2 1
MD<31..0>\I
23 22 21 20 19 18 17 16
31 30 29 28
J1
PART#352068-1
F VCC
29
RN157
SMD
RES_ARRAY_4
17
15 9 4
1 2 3 4
11 1 10 2 93 84
1 2 3 4
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 F1 F3 F5 F7 F9 F11 F13 F15 F17 F19 F21 F23 F25
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 F1 F3 F5 F7 F9 F11 F13 F15 F17 F19 F21 F23 F25
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25
30 26 3 21 18
12 7 1
E
25 20
10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10
6 7 8 5 6 7 8 5 7 8 5 6 7 8 5 8 6 7 8 5 6 7 8 5 8 5 6 7 8 5 6 7 6 6 5 7 7 8 7 6 5 6 5 6 7 8 5 8
43 42 39 38 37 36 35 34 32 31 30 29 28 25 24 23 11 8 7 6 5 4 3 2 157 156 155 154 153 152 151 150 33 22 12 158 21 13 14 15 17 159 16 19 20 149 148 44 18 144 143 145 142
AD<0> AD<1> AD<2> AD<3> AD<4> AD<5> AD<6> AD<7> AD<8> AD<9> AD<10> AD<11> AD<12> AD<13> AD<14> AD<15> AD<16> AD<17> AD<18> AD<19> AD<20> AD<21> AD<22> AD<23> AD<24> AD<25> AD<26> AD<27> AD<28> AD<29> AD<30> AD<31> C/BEB<0> C/BEB<1> C/BEB<2> C/BEB<3> PAR FRAMEB IRDYB TRDYB STOPB IDSEL DEVSELB PERRB SERRB CLK RSTB INTAB LOCKB EESK EEDO EEDI EECS TEST VSS<1> VSS<2> VSS<3> VSS<4> VSS<5> VSS<6> VSS<7> VSS<8> VSS<9> VSS<10>
14 8 3
11 6 0
D
4.7K
C
E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 ZPACK5X22A 2MM CPCI
NM93CS46
4.7K
R80
31 27 24 22 19 2
RN158
SMD 4.7K
RES_ARRAY_4
VCC PRE PE GND
VCC
1 1 13 10 0 5 2
9 26 40 51 65 80 104 120 147 160
CS SK DI DO
4 3 2 1
VCC
U1
99
4.7K R84 R85
0.1UF
LAD<0> LAD<1> LAD<2> LAD<3> LAD<4> LAD<5> LAD<6> LAD<7> LAD<8> LAD<9> LAD<10> LAD<11> LAD<12> LAD<13> LAD<14> LAD<15> LAD<16> LAD<17> LAD<18> LAD<19> LAD<20> LAD<21> LAD<22> LAD<23> LAD<24> LAD<25> LAD<26> LAD<27> LAD<28> LAD<29> LAD<30> LAD<31> LA<2> LA<3> LA<4> LA<5> LA<6> LA<7> LA<8> LA<9> LA<10> LA<11> LA<12> LA<13> LA<14> LA<15> LA<16> LA<17> LA<18> LA<19> LA<20> LA<21> LA<22> LA<23> LA<24> LA<25> LA<26> LA<27> LBEB<0> LBEB<1> LBEB<2> LBEB<3> LINTI1 LINTI2 LCLK LHOLD LHOLDA LRESETB BCLKO CSB<0> CSB<1> USER0/WAITOB USER1/LLOCKOB USER2/CS2B USER3/CS3B ADSB BLASTB LWR RDB WRB LRDYIB BTERMB ALE MODE
8 7 6 5
27 26 25 24
2B3<> 7F6<> 9F10<>
8 7 6 5
RN89
8 7 6 5
4.7K RN88
4.7K
RN87
4.7K RN85
8 7 6 5
VCC
4.7K
VCC
1 2 3 4
1 2 3 4
1 2 3 4
1 2 3 4
F
4.7K
VCC
2
8 7 6 5
RN83
8 7 6 5
4.7K RN82
4.7K
RN81
8 7 6 5
4.7K
ADDRESS BUS MA<11..0>\I U29
7 6 5 4
3 2 1 0
2B3< 7F9< 9G10<
E
RN93 47
1 2 3 4 8 7 6 5 5
AHC 540
15 19 16 19 17 19 18 19
U29
9
AHC 540
4 11 3
19
1 2 3 4
8 7 6 5
19
1
RN94 47
8
AHC 540
12 2 13
1
7
AHC 540
19
1
1
1
AHC 540
1
AHC 540
1
AHC 540
6
RN92
5 6 7 8
4.7K
1 2 3 4
PCI_INTB
9B2>
47
8 7 6 5
R13
PCI_RESETB CSB_ATLAS\I CSB_TETRA\I CSB_CPLD
9B10< 7E9< 2C3< 9B10<
U9
74FCT807
1
19
VCC
AHC 540
14
ATLAS_ALE\I
7E10<
D
C RN14 47
3 5 7 9 11 12 14 16 18 19 3 2 1 4 6 7 8 5
RDB\I WRB\I
2C3<7E9< 9H10< 2C3< 7E9< 9H10<
1
IN
O1 O2 O3 O4 O5 O6 O7 O8 O9 O10
CPLD_CLK
9D10<
VCC
C188
RN86
7 5 8 6
VCC
2 4 1 3
3.3 V
PCI-9050-1
C190 0.1UF C221
4.7K
RN91
7 8 6 5
VCC
4.7K
0.1UF
B
0.1UF C192 0.1UF 10UF 10UF C191 C228 C189
+
+
VCC
0.1UF
C227 0.1UF
C219 0.1UF
C226 0.1UF
C218
0.1UF
C220
2 1 3 4
VCC
B
PMC-Sierra, Inc.
A DRAWING TITLE=PCI_INTERFACE ABBREV=PCI_INTERFACE LAST_MODIFIED=Thu Jun 28 13:59:20 2001 10 9 8 7 6 5 4 3 DOCUMENT NUMBER: PMC-1991709 DOCUMENT ISSUE NUMBER: 1 TITLE: ATLAS TETRA PORT CARD PCI INTERFACE ENGINEER: RS 2 ISSUE DATE: 01/06/26 REVISION NUMBER: 2 PAGE:8 1 OF 12 A
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
8C3> 8C3> 8E2>
WRB\I RDB\I MA<11..0>\I
11 10 9 8 7 6 5 4 3 2 1 0
G VCC
G
4.7K
VCC
R16
SW1
2
PBNO
0.1UF
C183 0.1UF
RESET SWITCH 3.3 V F
8G1<> 7F6<> 2B3<>
C187
1
C155 0.1UF
3.3 V
F MD<31..0>\I
31
VCC VCC U8
0.1UF 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121
0.1UF
GND IO4/GSR IO4 VCCINT4 IO4 IO4 IO4 IO4 IO4 IO6 IO6 IO6 IO6 IO6 IO6 IO6 IO6 IO6 IO6 VCCIO6 IO6 IO8 IO8 GND12 TDO IO8 IO8 IO8 IO8 IO8 IO8 IO8 IO8 GND11 IO8 IO10 IO10 IO10 IO10 VCCIO5
C184 0.1UF
0.1UF
C181
C156
E
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7
D
8C1> 5F4>
CPLD_CLK PHY_SEL_CLK\I
6 5 4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
VCCIO1 IO4/GTS3 IO4 IO4/GTS4 IO4 IO2/GTS1 IO2 IO2/GTS2 IO2 VCCINT1 IO2 IO2 IO2 IO2 IO2 IO2 IO2 IO1 IO1 GND1 IO1 IO1 IO1 IO1 IO1 IO1 IO1 IO1 IO1 IO1 GND2 IO3 IO3/GCK1 IO3 IO3/GCK2 IO3 IO3 IO3 IO3 GND3
XC95216PQ160 10NS
GND10 IO10 IO10 IO10 IO10 IO10 IO10 IO10 IO12 IO12 GND9 IO12 IO12 IO12 IO12 IO12 IO12 IO12 IO12 IO12 GND8 GND7 IO11 IO11 IO11 IO11 VCCINT3 IO11 IO11 IO11 IO11 IO11 IO11 IO11 IO9 IO9 IO9 IO9 IO9 VCCIO4
120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
C157
E
D RN16 8 RN16 7 RN16 6 RN16 5
1 47
IADDR<0>\I IADDR<1>\I IWRENB\I ORDENB\I PHY_SEL_DAT<0>\I PHY_SEL_DAT<1>\I OCA\I ISOC\I OSOC\I
5D9< 5D9< 5D9< 5D9< 5B9> 5B9> 5D9> 5C9< 5D9>
47 2
3 47
47 4
47 R15
C VCCIO2 IO3/GCK3 IO3 IO3 IO5 VCCINT2 IO5 IO5 IO5 IO5 GND4 IO5 IO5 IO5 IO5 IO5 IO5 IO7 IO7 IO7 VCCIO3 IO7 IO7 IO7 IO7 IO7 IO7 IO7 IO7 GND5 TDI IO9 TMS IO9 TCK IO9 IO9 IO9 IO9 GND6
3.3 V
C
3.3 V
0.1UF
0.1UF
C182
C185
0.1UF
B
8C3> 8C3> 7E2<2F3< 7E9<2C3< 7E2<2F2<
CSB_CPLD PCI_RESETB JTAG_CLK\I RESETB\I
C186
3 2 1 0
41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
VCC
B TETRA_INTB\I ATLAS_INTB\I PCI_INTB
2C3> 7E6> 8C3<
J5
1 3 5 7 9 11 13 15 17 19
HEADER FOR ANALYSIS OF CPLD
A
NC CLK2 D15 CLK1 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 GND D0
2 4 6 8 10 12 14 16 18 20
J2 P_1 TDI P_2 TMS P_3 TCK P_4 TDO P_5 P_6
1 2 3 4 5 6
VCC
PMC-Sierra, Inc.
DOCUMENT NUMBER: PMC-1991709 DOCUMENT ISSUE NUMBER: 1 DRAWING: TITLE=PCI_INTERFACE ABBREV=PCI_INTERFACE LAST_MODIFIED=Thu Jun 28 13:59:24 2001 5 4 3 TITLE: ATLAS TETRA PORT CARD PCI INTERFACE ENGINEER: RS 2 ISSUE DATE: 01/06/26 REVISION NUMBER: 2 PAGE:9 1 OF 12 A
HP_LOGIC_ADAPTOR
8 7 6 5
HEADER FOR IN SYSTEM PROGRAMMING
10
9
8
7
RN72
1 2 3 4
6
4.7K
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
OPTICS 1
3.3 V
FB 0.1UF 10UF C194 0.1UF L2 C150 0.1UF C164 C193
3.3 V
OPTICS 3
FB L6 0.1UF C201
10UF
C158
+
+
50 OHM 3.3 V
0.01UF R48
TXD1P\I
2F9>
50 OHM 3.3 V
FB 0.1UF C197 0.01UF 49.9 R70
TXD3P\I
2D9>
49.9
G
10UF C162
FB 0.1UF C151 220 R47 L4
G
220 330 R67 R53
L7 10UF C199
C153
330
R46
C202
+
+
49.9
49.9
R49
13 14 15 16
HFCT5905 U2 VCCT VCCR GND GND GND HFCT5905 GND
6 2
TXDP TXDN RXDP RXDN SD TDIS
9 10 5 4 3 8
50 OHM 50 OHM 50 OHM
TXD1N\I RXD1P\I RXD1N\I SD1\I
2E9> 2F9< 2F9< 2F9<
13 14 15 16 11 12
HFCT5905 U6 VCCT VCCR GND GND HFCT5905 GND GND
6 2
TXDP TXDN RXDP RXDN SD TDIS
9 10 5 4 3 8
R71
50 OHM 50 OHM 50 OHM
TXD3N\I RXD3P\I RXD3N\I SD3\I
2D9> 2D9< 2D9< 2D9<
F
11 12
CHASS1 CHASS2 VEET
7
CHASS1 CHASS2 VEET
7
F
VEER
1 R56 150 R59 150 150 R58
VEER
1 R74 150 R76 150 150 R75
E E
3.3 V
OPTICS 2
FB L3 0.1UF 10UF C160 0.1UF
OPTICS 4
3.3 V
FB
+
C159
C165
10UF
C195
0.1UF
L9 C196 0.1UF C222
50 OHM D
C161 L5 10UF C163 0.01UF FB 49.9 R54 0.1UF
TXD2P\I
2E9>
+
3.3 V 3.3 V
220 R52 FB 0.1UF C198 220 R69 L8 10UF C200 0.01UF 49.9 R72
50 OHM
TXD4P\I
2C9>
D
C166
+
49.9
R55
330
R51
+
C203
C
13 14 15 16 11 12
HFCT5905 U3 VCCT VCCR GND GND HFCT5905 GND GND
6 2
49.9
TXDP TXDN RXDP RXDN SD TDIS
9 10 5 4 3 8
50 OHM 50 OHM 50 OHM
TXD2N\I RXD2P\I RXD2N\I SD2\I
2E9> 2E9< 2E9< 2E9<
13 14 15 16 11 12
CHASS1 CHASS2 VEET
7
HFCT5905 U7 VCCT VCCR GND GND GND HFCT5905 GND
6 2
TXDP TXDN RXDP RXDN SD TDIS
9 10 5 4 3 8
R73
330
R68
50 OHM 50 OHM 50 OHM
TXD4N\I RXD4P\I RXD4N\I SD4\I
2C9> 2D9< 2D9< 2C9<
C
VEER
1 R57 150 R61 150 150 R60
CHASS1 CHASS2 VEET
7
VEER
1 R82 150 R81 150 150 R77
B
B
PMC-Sierra, Inc.
A DRAWING TITLE=OPTICS_BLOCK ABBREV=OPTICS_BLOCK LAST_MODIFIED=Thu Jun 28 13:59:01 2001 10 9 8 7 6 5 4 3 DOCUMENT NUMBER: PMC-1991709 DOCUMENT ISSUE NUMBER: 1 TITLE: ATLAS TETRA PORT CARD OPTICS_BLOCK ENGINEER: RS 2 ISSUE DATE: 01/06/26 REVISION NUMBER: 2 PAGE:10 1 OF 12 A
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
6C4>
ISA<19..0>\I
H
3.3 V 3.3 V 3.3 V
15 41 65 91 4 11 20 27 54 61 70 77
3.3 V
15 41 65 91 4 11 20 27 54 61 70 77
U13 G
2 3 6 7 8 9 12 13 18 19 22 23 24 25 28 29 52 53 56 57 58 59 62 63 68 69 72 73 74 75 78 79 51 80 1 30 4 5 6 7 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
U16
0 1 2 3 4 5 6 7 8 9 10 11 12 16 17 18 19 32 33 34 35 36 37 44 45 46 47 48 49 50 81 82 99 100 31 83 89 85 84 88 87 93 94 95 96 92 97 98 14 86 64
G
0 1 2 3 4 5 6 7 8 9 10 11 12 16 17 18 19 32 33 34 35 36 37 44 45 46 47 48 49 50 81 82 99 100 31
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
VDD VDD VDD VDD
F ISRAMCLK0\I
A<0> A<1> A<2> A<3> A<4> A<5> A<6> A<7> A<8> A<9> A<10> A<11> A<12> A<13> A<14> A<15> A<16> LBO ADV CLK ADSC ADSP GW BWE BW1 BW2 BW3 BW4 CE1 CE2 CE3 FT OE ZZ
84036
5F4>
83 89 85 84 88 87 93 94 95 96 92 97 98
DQ<1> DQ<2> DQ<3> DQ<4> DQ<5> DQ<6> DQ<7> DQ<8> DQ<9> DQ<10> DQ<11> DQ<12> DQ<13> DQ<14> DQ<15> DQ<16> DQ<17> DQ<18> DQ<19> DQ<20> DQ<21> DQ<22> DQ<23> DQ<24> DQ<25> DQ<26> DQ<27> DQ<28> DQ<29> DQ<30> DQ<31> DQ<32> DQP<1> DQP<2> DQP<3> DQP<4>
2 3 6 7 8 9 12 13 18 19 22 23 24 25 28 29 52 53 56 57 58 59 62 63 68 69 72 73 74 75 78 79 51 80 1 30 0 1 2 3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
A<0> A<1> A<2> A<3> A<4> A<5> A<6> A<7> A<8> A<9> A<10> A<11> A<12> A<13> A<14> A<15> A<16> LBO ADV CLK ADSC ADSP GW BWE BW1 BW2 BW3 BW4 CE1 CE2 CE3 FT OE ZZ
84036
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ DQ<1> DQ<2> DQ<3> DQ<4> DQ<5> DQ<6> DQ<7> DQ<8> DQ<9> DQ<10> DQ<11> DQ<12> DQ<13> DQ<14> DQ<15> DQ<16> DQ<17> DQ<18> DQ<19> DQ<20> DQ<21> DQ<22> DQ<23> DQ<24> DQ<25> DQ<26> DQ<27> DQ<28> DQ<29> DQ<30> DQ<31> DQ<32> DQP<1> DQP<2> DQP<3> DQP<4>
VDD VDD VDD VDD
F
E
14 86 64
E
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
6B4> 6B4>
ISADSB\I ISRWB\I ISOEB\I ISRAMCLK1\I ISD<63..0>\I ISP<7..0>\I D
D
6B4> 5G4> 6G4<> 6D4<>
C
5 10 17 21 26 40 55 60 67 71 76 90
5 10 17 21 26 40 55 60 67 71 76 90
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
3.3 V 3.3 V
C
0.01UF
C148 0.01UF
C146 0.01UF
C147 0.01UF
C130 0.01UF
0.01UF
C126 0.01UF
C124 0.01UF
C129 0.01UF
C128 0.01UF
C127 0.01UF
C125 0.01UF
DECOUPLING FOR GS84036 B 1 CAP PER 2 POWER PINS B
C131
C149
DRAWING: TITLE=INGRESS_SRAM ABBREV=INGRESS_SRAM LAST_MODIFIED=Thu Jun 28 13:59:26 2001
PMC-Sierra, Inc.
A DOCUMENT NUMBER: PMC-1991709 DOCUMENT ISSUE NUMBER: 1 TITLE: ATLAS TETRA PORT CARD INGRESS SRAM ENGINEER: RS 10 9 8 7 6 5 4 3 2 ISSUE DATE: 01/06/26 REVISION NUMBER: 2 PAGE:11 1 OF 12 A
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
G
G
3.3 V 3.3 V
15 41 65 91
4 11 20 27 54 61 70 77
F ESA<19..0>\I
0 1 2 3 4 5 6 7 8 9 10 11 12 16 17 18 19 32 33 34 35 36 37 44 45 46 47 48 49 50 81 82 99 100 31
U12
F
6D8>
E
A<0> A<1> A<2> A<3> A<4> A<5> A<6> A<7> A<8> A<9> A<10> A<11> A<12> A<13> A<14> A<15> A<16> LBO ADV CLK ADSC ADSP GW BWE BW1 BW2 BW3 BW4 CE1 CE2 CE3 FT OE ZZ
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
VDD VDD VDD VDD
ESD<31..0>\I
DQ<1> DQ<2> DQ<3> DQ<4> DQ<5> DQ<6> DQ<7> DQ<8> DQ<9> DQ<10> DQ<11> DQ<12> DQ<13> DQ<14> DQ<15> DQ<16> DQ<17> DQ<18> DQ<19> DQ<20> DQ<21> DQ<22> DQ<23> DQ<24> DQ<25> DQ<26> DQ<27> DQ<28> DQ<29> DQ<30> DQ<31> DQ<32> DQP<1> DQP<2> DQP<3> DQP<4>
2 3 6 7 8 9 12 13 18 19 22 23 24 25 28 29 52 53 56 57 58 59 62 63 68 69 72 73 74 75 78 79 51 80 1 30 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
6F8<>
E
84036
5F4> 6C8> 6C8>
ESRAMCLK\I ESADSB\I ESRWB\I
83 89 85 84 88 87 93 94 95 96 92 97 98
ESP<3..0>\I
0 1 2 3
6E8<>
D
6C8>
D
ESOEB\I
14 86 64
C 3.3 V
5 10 17 21 26 40 55 60 67 71 76 90
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
C
DECOUPLING FOR GS84036
0.01UF C134 0.01UF C135 0.01UF C137 0.01UF C132 0.01UF C136 0.01UF
1 CAP PER 2 POWER PINS
C133
B
P1
B STRIP3
3
DRAWING: TITLE=EGRESS_SRAM ABBREV=EGRESS_SRAM LAST_MODIFIED=Thu Jun 28 13:58:59 2001 1 HOLE_SIZE= 100MIL
MOUNTING HOLE
STRIP2
2
STRIP1
CPCI ESD STRIP
1
PMC-Sierra, Inc.
DOCUMENT NUMBER: PMC-1991709 DOCUMENT ISSUE NUMBER: 1 TITLE: ATLAS TETRA PORT CARD EGRESS SRAM ENGINEER: RS ISSUE DATE: 01/06/26 REVISION NUMBER: 2 PAGE:12 2 1 OF 12 A
A
10
9
8
7
6
5
4
3
RELEASED REFERENCE DESIGN PMC-1991709 ISSUE 1
PM5351 S/UNI-155-TETRA
S/UNI 155 TETRA WITH S/UNI ATLAS REFERENCE DESIGN
10
LAYOUT
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
16
RELEASED REFERENCE DESIGN PMC-1991709 ISSUE 1
PM5351 S/UNI-155-TETRA
S/UNI 155 TETRA WITH S/UNI ATLAS REFERENCE DESIGN
11
BILL OF MATERIALS
Table 3 : Bill of Materials NO.
1
Part Name
49FCT3807_SOIC-BASE
Part Number
PERICOM PI49FCT807TS
Reference Descriptor
"U10, U14"
Qty
2
2
74AHC540_SOIC-BASE-V CC=3_3V
SN74AHC540DW
U29
1
3 4 5 6
74FCT807_SOIC-BASE 74XXX541_SOIC-VCC=3_ 3V 84036_TQFP-BASE "CAPACITOR-0.01UF, 50V, X7R_805"
IDT74FCT807BTSO PI74LPT541SA GSI GS84036T-166 DIGI-KEY -PCC103BNCT-ND
U9 U28 "U12, U13, U16" "C14, C109, C110, C112-C149, C151, C154, C161, C173, C175, C177-C179, C197, C198, C211, C215-C217, C223"
1 1 3 56
7
"CAPACITOR-0.1UF, 50V, X7R_805"
NEWARK -- 96F8740
"C2-C5, C7-C10, C107, C108, C111, C150, C152, C153, C155-C157, C159, C164-C171, C174, C176, C180-C188, C190, C192, C193, C196, C201-C207, C209, C210, C212-C214, C218-C222, C224, C226-C228"
62
8
"CAPACITOR-0.22UF, 50V, X7R_1210"
FAI 12105C224KATPS
"C1, C6, C172, C208"
4
9
"CAPACITOR-10UF, 16V, TANT TEH"
PCT3106CT-ND
"C11, C158, C160, C162, C163, C189, C191, C194, C195, C199, C200"
11
10
"CAPACITOR-4.7UF, 16V, TANT TEH"
DIGI-KEY -- PCT3475CTND DIGI-KEY -- PCT1476CTND DIGI-KEY -- U7472CT-ND
C225
1
11
"CAPACITOR-47UF, 6.3V, TANT TEH"
"C12, C13"
2
12
CHIP_RES_NETWORK_8_S MD-4.7K
RN6
1
13 14 15 16 17 18
HEADER3_100MIL-BASE HEADER6_100MIL-BASE HFCT5905 HP_LOGIC_ADAPTOR-BASE "INDUCTOR-FB, 50, FAIR RITE" "LED-RED, PCB .29 RIGHT
PZC36SAAN PZC36SAAN HFCT-5905E DIGI-KEY S2012-36-ND FAIR RITE - 2743019447 DIGI-KEY -- L20361-ND
J3 J2 "U2, U3, U6, U7" J5 L2-L9 D1-D4
1 1 4 1 8 4
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
17
RELEASED REFERENCE DESIGN PMC-1991709 ISSUE 1
PM5351 S/UNI-155-TETRA
S/UNI 155 TETRA WITH S/UNI ATLAS REFERENCE DESIGN
NO.
Part Name
ANGLE"
Part Number
Reference Descriptor
U11 U1 Y1
Qty
19 20 21
LT1121CST_SOT-3.3V NM93CS46_DIP8-BASE "OSC_CMOS_8PIN_DUAL-H CMOS, 19.44A"
LT1121CST-3.3 NM93CS46EN MMD MB3020HH19.440MH Z MMD MB3100HH50.000MH Z DIGIKEY -- CKN4002-ND PCI9050-1
1 1 1
22
"OSC_CMOS_8PIN_DUAL-H CMOS, 50.00A"
Y2
1
23 24 25 26 27 28 29 30 31 32 33 34 35
PBNO_RIGHT_ANGLE-BASE PCI9050_PQFP-BASE "RESISTOR-1.0K, 5%, 805" "RESISTOR-100, 5%, 805" "RESISTOR-10K, 5%, 805" "RESISTOR-150, 5%, 805" "RESISTOR-158, 1%, 805" "RESISTOR-180, 5%, 805" "RESISTOR-2.2, 5%, 805" "RESISTOR-220, 5%, 805" "RESISTOR-330, 5%, 805" "RESISTOR-4.7, 5%, 805" "RESISTOR-4.7K, 5%, 805"
SW1 U5 "R39, R64" "R5, R6, R11, R12" "R40, R41, R43-R45" "R56-R61, R74-R77, R81, R82" "R1-R4, R7-R10" R18-R21 R83 "R47, R52, R67, R69" "R46, R51, R53, R68" R14 "R16, R42, R62, R63, R65, R79, R80, R84, R85"
1 1 2 4 5 12 8 4 1 4 4 1 9
36 37 38 39
"RESISTOR-47, 5%, 805" "RESISTOR-49.9, 1%, 805" RES_ARRAY_4_SMD-10 RES_ARRAY_4_SMD-4.7K
"R13, R15, R37, R38, R66, R78" "R48, R49, R54, R55, R70-R73" "RN1-RN5, RN8-RN13, RN73, RN90" "RN15, RN72, RN78-RN89, RN91, RN92"
6 8 13 16
40
RES_ARRAY_4_SMD-47
"RN7, RN14, RN16, RN25-RN30, RN52RN62, RN74-RN77, RN93, RN94"
26
41 42 43 44
SUNIATLAS_SBGA-BASE SUNITETRA_SBGA-BASE XC95216PQ160-10NS ZPACK5X22FH_ASCPCI_2 MM
PM7324 PM5351 XC95216-10PQ160C 352068-1
U15 U4 U8 J1
1 1 1 1
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
18
RELEASED REFERENCE DESIGN PMC-1991709 ISSUE 1
PM5351 S/UNI-155-TETRA
S/UNI 155 TETRA WITH S/UNI ATLAS REFERENCE DESIGN
12
VHDL CODE
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use work.all;
entity Atlas_Tetra is port ( ma: inout std_logic_vector(11 downto 0);--PCI Address Bus md: inout std_logic_vector(31 downto 0);--PCI Data Bus wrb: in std_logic; --PCI Write Enable rdb: in std_logic; --PCI Read Enable reset_switch: in std_logic; --Reset Switch Input cpld_clk: in std_logic; --33MHz clock phy_sel_clk: in std_logic; --50MHz clock csb_cpld: in std_logic; --CPLD Chip Select osoc: in std_logic; --Ingress Output Start of Cell atlas_intb,tetra_intb: in std_logic; --PMC device interrupts phy_sel_dat: in std_logic_vector (1 downto 0);--PHY select bits oca: in std_logic; --Ingress Output Cell Available pci_resetb: out std_logic; --PCI Interface Reset jtag_clk: out std_logic; --JTAG Clock out resetb: out std_logic; --Reset output iaddr: out std_logic_vector(1 downto 0);--Egress Input PHY address iwrenb: out std_logic; --Egress Input Write Enable ordenb: out std_logic; --Ingress Output Read Enable isoc: out std_logic; --Egress Input Start of Cell HP_out: out std_logic_vector(9 downto 0); pci_intb: out std_logic); --PCI Interface interrupt end Atlas_Tetra; architecture vhdl of Atlas_Tetra is signal pci_data: begin --PROCESS GLOBAL_RESET: --This process will reset the ATLAS,TETRA,and PLX PCI Bridge global_reset: process(phy_sel_clk,reset_switch) begin if phy_sel_clk'event and phy_sel_clk='1' then if reset_switch = '0' then resetb<='0'; pci_resetb<='0'; else resetb<='1'; pci_resetb<='1'; std_logic_vector(31 downto 0);
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
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RELEASED REFERENCE DESIGN PMC-1991709 ISSUE 1
PM5351 S/UNI-155-TETRA
S/UNI 155 TETRA WITH S/UNI ATLAS REFERENCE DESIGN
end if; end if; end process global_reset; --PROCESS RW_DATA: --This process will assign the 2 LSB's from the data bus to the --IADDR(1..0) lines rw_data: process(cpld_clk,pci_data(31 downto 0),wrb,csb_cpld) begin if cpld_clk='1' and cpld_clk'event then if csb_cpld='0' then if wrb='0' then pci_data(31 downto 0)<=md(31 downto 0); iaddr(1 downto 0)<=md(1 downto 0); end if; else md(31 downto 0)<=(others=>'Z'); end if; end if; end process rw_data; --IWRENB and ORDENB are switched with OCA pci_intb<='Z'; jtag_clk<=cpld_clk; HP_out(9)<= phy_sel_clk; ordenb<=oca; iwrenb<=oca; HP_out(7)<= oca; --ISOC is switched with OSOC isoc<=osoc; HP_out(8)<= osoc; ma<=(others=>'Z');
end vhdl;
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
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RELEASED REFERENCE DESIGN PMC-1991709 ISSUE 1
PM5351 S/UNI-155-TETRA
S/UNI 155 TETRA WITH S/UNI ATLAS REFERENCE DESIGN
13
EEPROM CONTENTS The following table presents the contents of the EEPROM used for the PLX device initialization. Values are in little endian format.
Table 5 : EEPROM Contents EEPROM Offset (Hex) Value (Hex) 0 2 4 6 8 A C E 10 12 14 16 18 1A 1C 1E 20 22 24 26 28 2A 9050 10B5 0660 0000 7324 11F8 FFFF 00FF 0FFF C000 0FFF F000 0FFF FC00 0000 0000 0FFF 0000 0000 0001 0000 4001 PLX Register Device ID Vendor ID Class Code ClassCode Subsystem ID Subsystem Vendor ID Max Latency and Min Grant (not loadable) Interrupt Pin MSW of Address Space 0 Range LSW of Address Space 0 Range MSW of Address Space 1 Range LSW of Address Space 1 Range MSW of Address Space 2 Range LSW of Address Space 2 Range MSW of Address Space 3 Range LSW of Address Space 3 Range MSW of Expansion Rom Range LSW of Expansion Rom Range MSW of Address Space 0 Remap LSW of Address Space 0 Remap MSW of Address Space 1 Remap LSW of Address Space 1 Remap
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
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RELEASED REFERENCE DESIGN PMC-1991709 ISSUE 1
PM5351 S/UNI-155-TETRA
S/UNI 155 TETRA WITH S/UNI ATLAS REFERENCE DESIGN
EEPROM Offset (Hex) Value (Hex) 2C 2E 30 32 34 36 38 3A 3C 3E 40 42 44 46 48 4A 4C 4E 50 52 54 56 58 5A 5C 5E 60 62 0001 0001 0000 0000 0000 0000 5481 4100 2081 C0C0 0090 A840 0000 0000 0000 0000 0000 2001 0000 4801 0001 0005 0000 0000 0000 0000 0002 44D2
PLX Register MSW of Address Space 2 Remap LSW of Address Space 2 Remap MSW of Address Space 3 Remap LSW of Address Space 3 Remap MSW of Expansion Rom Remap LSW of Expansion Rom Remap MSW of Space 0 Bus Descriptor LSW of Space 0 Bus Descriptor MSW of Space 1 Bus Descriptor LSW of Space 1 Bus Descriptor MSW of Space 2 Bus Descriptor LSW of Space 2 Bus Descriptor MSW of Space 3 Bus Descriptor LSW of Space 3 Bus Descriptor MSW of Expansion Rom Bus Descriptor LSW of Expansion Rom Bus Descriptor MSW of CS0 Register LSW of CS0 Register MSW of CS1 Register LSW of CS1 Register MSW of CS2 Register LSW of CS2 Register MSW of CS3 Register LSW of CS3 Register MSW of Interrupt Control/Status LSW of Interrupt Control/Status MSW of EEPROM and Misc. Control LSW of EEPROM and Misc. Control
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
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RELEASED REFERENCE DESIGN PMC-1991709 ISSUE 1
PM5351 S/UNI-155-TETRA
S/UNI 155 TETRA WITH S/UNI ATLAS REFERENCE DESIGN
EEPROM Offset (Hex) Value (Hex) 64 - 7F FFFF
PLX Register Unused
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
23
RELEASED REFERENCE DESIGN PMC-1991709 ISSUE 1
PM5351 S/UNI-155-TETRA
S/UNI 155 TETRA WITH S/UNI ATLAS REFERENCE DESIGN
NOTES
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
24
RELEASED REFERENCE DESIGN PMC-1991709 ISSUE 1
PM5351 S/UNI-155-TETRA
S/UNI 155 TETRA WITH S/UNI ATLAS REFERENCE DESIGN
CONTACTING PMC-SIERRA, INC. PMC-Sierra, Inc. 105-8555 Baxter Place Burnaby, BC Canada V5A 4V7 Tel: Fax: (604) 415-6000 (604) 415-6200 document@pmc-sierra.com info@pmc-sierra.com apps@pmc-sierra.com Tel: (604) 415-4533 Fax: (604) 415-6206 http://www.pmc-sierra.com
Document Information: Corporate Information: Application Information: Web Site:
None of the information contained in this document constitutes an express or implied warranty by PMC-Sierra, Inc. as to the sufficiency, fitness or suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchantability, performance, compatibility with other parts or systems, of any of the products of PMC-Sierra, Inc., or any portion thereof, referred to in this document. PMC-Sierra, Inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not limited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement. In no event will PMC-Sierra, Inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or reliance upon the information, whether or not PMC-Sierra, Inc. has been advised of the possibility of such damage. (c) 2001 PMC-Sierra, Inc. PMC-1991709 (R1) ref PMC-1971240 (R7) Issue date: September 2001
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